Impedance calibration circuits and semiconductor devices including impedance calibration circuits find application in a variety of technologies, including in avoiding/reducing impedance mismatch on signal transmission lines. As will be appreciated by a person skilled in the art, avoiding/reducing impedance mismatch is important for the power transfer efficiency of a signal transmission link. This is particularly relevant for multi-gigabyte/s rates of signal transmission, in order to preserve signal integrity. If the bit period is shorter than the flight time, as in high speed multi-gigabytes/s transmission links, echoes of previous pulses may arrive at the receiver on top of the main pulse, thus corrupting the received signal. The signal integrity may be evaluated, for example, in the degradation of the eye diagram of a signal transmission link at a given signal transmission rate. Typically, acceptable eye specification conditions are set by different transmissions standards.
One conventional impedance calibration circuit 100 is shown in FIG. 1. In the calibration circuit 100, an input from a reference voltage generator (VBG) is provided to an opamp 101, which through an analog loop forces a current VBG/REXT through transistor device 102 and precise external resistor REXT in an external ground arm 106, and this current is mirrored into transistor device 104 and an internal programmable resistor 116, which is coupled to internal chip ground, and hence called “internal” arm 108. The voltages at an REXT node and an RINT node 110, 112 respectively are provided as negative and positive inputs of a comparator 114 to generate an output signal COMPOUT to a calibration logic (not shown). The calibration logic generates calibration codes to be used in the RINT impedance calibration (programmable resistor 116), which is a scaled up version of the actual driver impedance calibration unit (not shown) to which the same calibration code is simultaneously provided. As will be appreciated by a person skilled in the art, a scaled up version of the driver impedance calibration unit is typically incorporated into the calibration circuit to avoid the large currents that would otherwise be associated with incorporating directly the actual impedance calibration unit for a typical transmission line.
The calibration scheme implemented by the impedance calibration circuit 100 may improperly calibrate the impedance that should match the characteristic impedance owing to the noise present on supply/ground lines. More particularly, this calibration scheme cannot handle a number of noise sources, including ground bounce, periodic noise, and packet start/stop noise. For example, in current-mode driver voltage-sensing high speed links, such as Universal Serial Bus (USB), large currents are dumped into the ground rail at the data rate, resulting in ground bounce. Furthermore, digital grounds may be merged with analog grounds to reduce the pin count.
Periodic noise may originate, for example, from one or more Phase Locked Loops (PLLs) employed on high speed links, or from the digital circuitry, e.g., high speed data switching, clock buffers, etc. Packet Start/Stop Noise may be associated with burst mode transmission and inter-packet delay. FIGS. 2A-2D are respective graphs illustrating the adverse effects of chip supply noise and internal chip ground noise in the above-described calibration scheme. More particularly, in FIG. 2A, the differences of the voltages at the internal and external nodes (curves 200, 202 respectively) are shown due to the internal and external ground mismatch. FIGS. 2B-2D show the chip supply, external ground, and internal chip ground corresponding signals respectively, illustrating the contributions of the chip supply noise and internal chip ground noise (i.e., Ground Bounce Noise) to the difference between the voltages at nodes 112, 110 (FIG. 1) respectively. As will be appreciated, while the supply noise and the Ground Bounce Noise appear to be of similar amplitude, their respective contributions to noise on REXT & RINT Nodes are different. The Ground Bounce Noise is coupled directly to the REXT and RINT nodes through a resistor, while the supply noise gets shaped by the analog loop and transistor devices.